Content addressable memory cell and array are well known in the art. See, for example, U.S. Pat. No. 6,078,513; 5,949,696; 5,930,161; and 5,051,943. A differential non-volatile content addressable memory cell and array is also well known in the art. See, for example, U.S. Pat. No. 6,005,790.
Referring to FIG. 1, there is shown a binary differential volatile content addressable memory array 10 of the prior art. In this memory array 10, a differential content addressable memory cell, such as cell 12a, is comprised of pair of SRAMs, each storing data complementary to one another. The cell 12a is queried by comparing the data on the compare data line 18a and the compare data bar line 18b to the data stored in the cell 12a. The match line 14 is pre-charged to a pre-determined voltage. During the compare event, all the rows are compared at the same time and each match line 14 that fails the comparison of the compare data with the stored data in each row is pulled down. The result of the comparison in each row is stored in a latch 16. The array 10 is a binary content addressable memory array, in that each cell 12 stores a binary state. Thus, each cell 12 stores either the state of “10” or “01.” Each cell 12, thus has two states. Although the content addressable memory array 10 is of high speed because the memory cell 12 uses an SRAM as the storage element, it is volatile and further has high power requirements.
Referring to FIG. 2, there is shown a ternary content addressable memory array 20 of the prior art. The ternary content addressable memory array 20 is similar to the binary content addressable memory array 10 of the prior art shown in FIG. 1. The array 20 comprises a plurality of memory cells 22 arranged in the plurality of rows and columns. Each memory cell 22 has two storage elements 12a and 12b for storing the data bits and two storage elements 13a and 13b for storing the mask bit 13. Each of the storage elements 12a and 12b uses an SRAM cell. Data that needs to be compared during the compare event is driven in the compare data line 18a and the compare data bar line 18b. These lines are supplied to the data bit storage elements 12a and 12b from which either the state of “10” or “01” are stored just like that shown and described in FIG. 1. As for the mask bit 13, the mask bit 13 stored in the mask bit storage elements 13a and 13b can be in either the state of “11” or “00.” If the mask bit 13 is in one state, such as “11,” then that storage is used to mask the bit 13 from the compare event as to make it a “don't care” comparison. Again, similar to the array 10, the match line 14 is pre-charged to a pre-determined voltage. During the compare event, all the rows are compared at the same time and each match line that fails the comparison of the compare data with the stored data is pulled down. Only those bits participating in the compare event that are not masked by the respective mask bits are compared. The final comparison results are stored in latches 16. Similar to the array 10, the array 20, using SRAM storage elements has the properties of high speed but also high power and volatility.
Referring to FIG. 3, there is shown an example of a differential non-volatile content addressable memory cell 30 of the prior art, as exemplified by U.S. Pat. No. 6,639,818. In this differential non-volatile content addressable memory cell 30, a pair of non-volatile transistors 32a and 32b form the content addressable memory cell 30. Each of the non-volatile memory transistors 32 has a first terminal and a second terminal with a channel region therebetween. The first terminal is connected to a compare data line 18a or a compare data bar line 18b. The second terminal is connected to a common match line 14. A floating gate, closer to the second terminal or the match line 14, than to the first terminal, controls a portion of the channel region with a control gate controlling the conduction of another portion of the channel region. A word line 34 is connected to the control gate of each of the non-volatile transistor elements 32a and 32b. The non-volatile content addressable memory cell 30 is not a ternary cell, because it cannot mask each individual bit in the array.
Although the differential non-volatile content addressable memory cell 30 (and the array in which these cells 30 are formed) satisfy the criteria of non-volatility, and density, they suffer from having a leakage current. During the match event, there is a DC current leakage from the driven match line through the unmatched cells since the driven data lines are not isolated from the conducting channel. The compare data line 18a and the compare data bar line 18b are connected directly to the channel. Since the match event for all rows occur simultaneously, this increases a power consumption problem. Further, since there needs to be at most only a single unmatched cell in an entire row to cause a mismatch condition for that row, the sensing amplifiers of the array that contains the cells 30 must be able to detect the pre-charged match line 14 moving only slightly, if it moves at all, during the compare event. This slows down the event detection, in that the sense amplifiers must wait to detect the possibility of a slight movement condition of the match line 14. Furthermore, there are sensing reliability issues that impose limitations on the array architecture.
Hence, there is need for differential non-volatile content addressable memory cell that can detect reliably at high speed and consume low power.